(1) Field of the Invention
The present invention relates to a multilevel programming method for a semiconductor storage, in particular, for floating gate type nonvolatile semiconductor storage of a virtual ground memory array.
(2) Description of the Related Art
In recent years, virtual ground type flash memory devices aiming for high packing density have drawn attention, such as for example, `A New Cell Structure for Sub-quarter Micron High Density Flash Memory` (IEDM Technical Digest, pp.269-270, 1995), and an ACT (Asymmetrical Contactless Transistor) type flash memory disclosed in `An investigation of a sensing method of an ACT type flash memory` (ICD97-21, p.37, 1997, a technical report of The Institute of Electronics, Information and Communication Engineers).
In such an ACT type flash memory, programming and erasing operations are implemented based on the FN (Fowler-Nordheim) tunnel effect, and it is expected to be used for data storage type.
Referring now to FIGS. 1 and 2, the ACT type flash memory will be described.
An ACT type flash memory uses the FN tunnel effect when programming and erasing as stated above, and has a virtual ground array configuration in which each bit line is shared between two memory cells. In this way, in an ACT type flash memory, the bit lines are shared and formed of a diffusion layer to thereby reduce the number of contacts and enable a remarkable reduction of the array area, which leads to high integration.
Next, an ACT type flash memory device, as sectionally shown in FIGS. 2A and 2B, has, in order from the top, a control gate WL, an inter-layer insulating layer, a floating gate FG and a bit line (diffusion layer) arranged in a layered manner. The common bit line formed under and between the adjacent floating gates FG has different donor densities between the drain and source sides.
In FIG. 1 where ACT type flash memory cells are arranged in an arrayed configuration, MBLx represents main bit lines, SBLx represents sub-bit lines formed of a diffusion layer, WLx represents word lines, SGx represents gate selection signal lines, CONTACT represents a contact point between a main bit line and a sub-bit line (belonging to different layers).
Next, programming and erasing operations for an ACT type flash memory using the FN tunnel effect will be described.
First, programming the ACT type flash memory (see FIG. 2A) is performed with a negative voltage of -8 volts (`volts` will be abbreviated hereinbelow as `V`) applied to gate WL and a positive voltage of 5 V applied to the drain side. By this voltage application, the FN tunnel effect occurs on the drain side so that electrons are extracted from floating gate FG to the drain side. This extraction of electrons lowers the threshold level, which means that programming is implemented.
An erase operation is performed with a high voltage (+10 V) applied to gate WL and a negative voltage (-8 V) applied to the bit lines and the substrate (P-portion) so as to generate the FN tunnel effect between the channel layer and floating gate FG to thereby inject electrons into the floating gate FG. This injection of electrons raises the threshold level, which means that erasing is implemented.
The operating principle of one ACT type flash memory (memory cell) M schematically shown in FIG. 3 will be described more detailedly.
In an ACT type flash memory M, a control gate 100, a inter-layer insulating layer 101, a floating gate 102 and a tunnel oxide film 103 are formed in layers and this layered structure is placed over and between a drain 105 and source 106 formed within a substrate 104. As already mentioned, drain 105 and source 106 have different donor densities from each other.
In the beginning, for a program operation, or to extract electrons from floating gate 102, a negative voltage Vnw (-8 V) is applied to control gate 100, a positive voltage Vpp (+5 V) is applied to drain 105 and source 106 is set floating. Under these conditions, electrons are drawn from floating gate 102 by the FN tunnel effect, and thereby the threshold level of memory cell M is lowered to about 1.5 V.
For an erase operation, or to inject electrons into floating gate 102, a positive voltage Vpe (+10 V) is applied to control gate 100, a negative voltage Vns (-8 V) is applied to source 106 and drain 105 is set floating. Under the conditions electrons are injected into floating gate 102 by the FN tunnel effect and thereby the threshold level of memory cell M is raised over about 4 V.
A flash memory as above which uses the FN tunnel effect for both program and erase operations is called an FN--FN operating flash memory.
For a read operation, 3 V is applied to control gate 100, 1 V is applied to drain 105, 0 V is applied to source 106. The current flowing through cell M under the conditions, is detected by an unillustrated sensing circuit to read out the data.
The application of voltage for the above operations is summarized in Table 1.
TABLE 1 Application of voltage to a conventional flash memory Control Gate Drain Source P-type Well Program -8 V 5 V Open 0 V Erase 10 V Open -8 V -8 V Read 3 V 1 V 0 V 0 V
In the field of memory technology, as an attempt to aim at higher integration, multilevel techniques for introducing three or more threshold levels to each memory cell have been published. Examples of the multilevel technology include the following methods.
A first conventional method (conventional method 1) is disclosed in 1997 ISSCC Dig. Tech. Papers, pp36-37 "A 98 mm.sup.2 3.3V 64 Mb Flash Memory with FN-NOR Type-4level cell" and in Japanese Patent Application Laid-Open Hei 6 No.177,397.
A second conventional method (conventional method 2) is disclosed in 1997 ISSCC Dig. Tech. Papers, pp32-33 "A 3.3V 128 Mb Multilevel NAND Flash Memory For Mass Storage Applications" and in Japanese Patent Application Laid-Open Hei 9 No.7,383.
In the conventional method 1, an FN-NOR type flash memory is used. The flowchart of the algorithm for programming memory cell M is shown in FIG. 4. In this case, for data `11`, `10`, `01`, programming pulses are simultaneously applied by applying different voltages to drains 105, making use of the threshold level voltage-to-time characteristic shown in FIG. 5. Based on this characteristic, each cell is programmed so as to have a voltage level falling within one of the threshold levels in the distribution shown in FIG. 6 (Step S20).
As shown in FIG. 6, data `00` is the erased state. Subsequently, a verify operation (data verification after programming) (Step S21) is performed in two stages.
At the first stage, the reference voltage (the standard voltage with which comparison is made) is set at around 2.3 V, for example, so as to judge whether the threshold level falls within the `11` and `10` states or within the `01` and `00` states (see FIG. 6).
Next, at the second stage, a different operation will be effected based on the sensed result from the first stage. When the sensed result from the first stage falls within the `11` and `10` states, then the reference voltage is set at 1.3 V, for example, so as to determine whether the threshold level is `11` or `10`. When the sensed result from the first stage falls within the `01` and `00` states, then the reference voltage is set at 3.3 V, for example, so as to determine whether the threshold level is `01` or `00`.
The above operations, that is, application of the programming pulses and verification, are repeated based on the verification result until the desired threshold level is obtained (Steps 20 and 21 in FIG. 4). Generally, the characteristics of the change in threshold level fluctuates when the FN tunnel effect is used, so that a pulse width shorter than that meeting the actual characteristic is used. That is, pulse applications (voltage application to the bit lines) are stopped in the order in which programming is completed, so as to set the designated threshold levels whilst preventing the lowering of the threshold levels.
Conventional method 2 is used in an NAND type flash memory. FIG. 7 shows a flowchart of the algorithm for this method. FIG. 8 shows a distribution chart of the threshold levels after programming.
In the case of this NAND type flash memory, as shown in FIGS. 7 and 8, programming is commenced from the level closest to the erased state.
In the beginning, data `10` around 0.6 V is determined (Steps S30 and S31). Then, data `01` around 1.8 V (Steps S32 and S33) and data `00` around 3.0 V (Steps S34 and S35) are written in, in this order.
In this NAND type flash memory, a technique whereby the voltage of gate 100 is increased whenever a pulse is applied is used. Therefore, it is preferred that data, i.e., threshold level should be determined from the state closest to the erased state.
When the multilevel programming method used for the NAND type flash memory (FIGS. 7 and 8) is adopted as the method for introducing three or more threshold levels to an ACT type flash memory, or more specifically, or when the data is determined sequentially from the state closest to the erased state `11`, the following problems occur.
FIG. 11 shows a flowchart of the algorithm when the multilevel programming method which is used for the NAND type flash memory is applied to an ACT type flash memory configured as shown in FIG. 9. FIG. 10 shows the distribution of the threshold levels after programming the ACT type flash memory. Here, data `00` is the erased state, and programming is performed with verification, from data `01`, which is closest to the erased state (Steps S40 and 41). During this, cells M having data other than `01` will not be written into. If all the memory cells M have data other than `01`, no programming is effected in this initial stage so that all the memory cells remain in the erased state.
The range of the threshold level of cell M having data `01` is between 2.6 V and 3 V as shown in FIG. 10.
Subsequently, programming of data `10` and then data `11` is effected with verification (Steps S42 to S45).
For example, a case where memory cell M02 is read out for verification (including read operation) will be considered. This operation is performed with +3 V applied to word line (WL0), +1 V applied to bit line BL2 (on the drain side) and 0 V applied to bit line BL3 (on the source side). In this case, the following three situations will occur.
In the above case, bit line BL1 is set at +1 V so as not to allow for a roundabout current to flow through cell M01. Here, the bit lines are provided as units of four bits (BL0 to BL3, BL4 to BL7 and the like), but the detailed description is omitted.
First, as shown in FIG. 12, when cells M01 and M03 adjacent to cell M02 have data `00`, of which the threshold level is higher than that of cell M02, current I01 flows correctly so that an unillustrated sensing circuit will detect the correct threshold level.
On the other hand, as shown in FIG. 13, when M00 and M01 have data `11`, of which the threshold level is lower than that of cell M02, in reading out data of cell M02, a roundabout current Ir, other than the normal current I01 flowing through cell M02, will flow by way of cells M00 and M01. Because bit line BL1 is also applied with 1 V, normally no roundabout current Ir should occur. However, as already mentioned, an ACT type cell uses bit lines BL formed of a diffusion layer so that it presents high resistance, which may lower the potential to 0.5 V, for example, due to voltage drop. This is why a roundabout current Ir as above arises.
In this way, if an increased current (I01+Ir), which is greater than the normal current I01, is detected at the node on bit line BL2, apparently the threshold level of cell M02 is erroneously detected as a lower value by an unillustrated sensing circuit. When this situation is observed it is as if the distribution of the threshold level were shifted lower (in the direction of arrow 1 in FIG. 14) and widening its range, as shown in FIG. 14.
Further, also when cells M00 and M01 have data `00` (which has the greater threshold than that of cell 02) and cells M03 and M04 have data `11` (which has the lower threshold than that of cell 02) as shown in FIG. 15, erroneous detection can occur.
In this case, no current flows on the cell M01 side. However, because bit line BL5 is set at 1 V (the same voltage applied to BL1 in the block BL0 to BL3 is applied correspondingly to BL5 in the block BL4 to BL7), a roundabout current Ij will flow through M03 and M04 in which the threshold level is lower. As a result, the potential of bit line BL3 rises over 0 V, which is the normal voltage.
In this case, the current (Ibl=I01+Ij) for cell M02 at the node of bit line BL2 decreases due to the backgating effect. In this situation, the threshold level of cell M02 is apparently mis-detected to be shifted higher than the correct threshold level of cell M02 (in the state where only current I01 flows). This situation will be detected as if the distribution of the threshold level (the hatched area) were widened in the direction of arrow 2 as shown in FIG. 14.
In this way, when the data is determined from the state closest to the erased state in order to write multi-levels of data to an ACT type flash memory, the distribution of the threshold level should normally fall within the range of 0.4 V wide from 2.6 V to 3.0 V, but the range (fluctuation) of the threshold level will be detected spreading as wide as 1.0 V from 2.2 V to 3.2 V (see FIG. 14).
In this case, taking into account that the readout voltage for distinguishing between the threshold levels of `10` and `01` is set at about 2.3 V (corresponding to the readout voltage 2 in FIG. 10), this widening of the distribution of the threshold level will cause the erroneous reading, which degrades reliability.
In FIG. 14, the case of data `01` was explained, a similar widening of the distribution of the threshold level occurs in the case of data `10`.
Next, description will be made of the case where the multilevel programming method used in the aforementioned FN-NOR type flash memory is applied to an ACT cell type.
FIG. 16 shows a flowchart of the algorithm of this case. In this method, programming is performed simultaneously for all the levels (Steps S50 and 51). However, the programming characteristics generally differ between cells M, so that the time required for one cell to gain the designated level will be different from others. The worst case is that where the cell having data `01` reaches its threshold level first. In this case, the distribution (range) of each threshold level widens in a similar manner to the above case, again causing erroneous reading.